The present invention relates to a graphic processor used for computer graphics, and more particularly to that and a bit-built method applied therein for superimposing bit-map data of an image on a video memory.
FIG. 9 is a block diagram illustrating a graphic processor disclosed in a Japanese patent application laid open as a Provisional Publication No. 311382/'89 developed for overwriting or superimposing bit-map data of a line pattern on a video memory, comprising;
a line pattern shift register 901 of 16 bits wherein are prepared bitmap data of a line pattern for drawing a line image, which are shifted up bit by bit synchronized with a shift clock, logic of a bit shifted out being returned as a lowest significant bit to the line pattern shift register 901, PA1 a repeat counter 902 consisting of a four-bit down-counter for supplying the shift clock when its count value becomes `0`, PA1 a zoom register 903 wherein a magnification factor is delivered through a data-bus DB, the magnification factor being supplied to the repeat counter 902 as a load clock, PA1 a memory controller 904 for outputting a count clock signal to be supplied to the repeat counter 902 in order to control timings of data read-out from the line pattern shift register 901, and outputting a write enable signal WE (enable at logic LOW) of the video memory (not shown in FIG. 1) in order to control timings of data writing into the video memory, PA1 a transparency register 905 wherein registered a transparency flag indicating whether the bit-map data are to be superimposed or overwritten written on the video memory, and PA1 a transparency controller 906 having a gate 907 and a selector 908, the gate 907 outputting AND logic of each bit shifted out from the line pattern shift register 901 and inverse logic of the write enable signal WE, and the selector 908 selecting output of the gate 907 when the transparency flag in the transparency register 905 is ON and selecting inverse logic of the write enable signal WE when the transparency flag is OFF. PA1 discriminating whether data of a pixel of the image are the same or not with data of a designated transparent color; and PA1 writing data of the pixel into a line buffer in order only when data of the pixel are discriminated to be different from data of the designated transparent color. PA1 writing data of a pixel of the image in a line buffer at an address indicated by an address value; PA1 discriminating whether data of the pixel are the same or not with data of a designated transparent color; and PA1 incrementing the address value only when data of the pixel are discriminated to be different from data of the designated transparent color. PA1 a video memory for storing pixel data of the first and the second images; PA1 a reading address generator for generating a reading .chi.-address and a reading .psi.-address for reading out pixel data of the first image from the video memory, said reading .chi.-address beginning with a first beginning .chi.-address and incremented every time when data of a pixel are read out when data of each line of the first image are read out from the video memory; PA1 an offset counter for counting an offset value of the reading .chi.-address of data of each of pixels read out of a line of the first image from the first beginning .chi.-address; PA1 a transparent color register for storing data of a designated transparent color; PA1 a transparency discriminator for discriminating whether data of a pixel read out of the video memory are the same or not with data of the designated transparent color; PA1 a line buffer capable for storing pixel data of one line of the first image; PA1 an offset buffer for storing the offset value of each of pixels whereof data are stored at corresponding addresses of the line buffer; PA1 a buffer controller, said buffer controller controlling the offset counter to increment the offset value every time when data of a pixel of a line of the first image are read out and to reset the offset value to zero every time when data of a line of the first image are read out, and storing data of the pixel and the offset value into the line buffer and the offset buffer, respectively, in order when data of the pixel are discriminated to be different from data of the designated transparent color by the transparency discriminator; PA1 a writing address generator for generating a writing .chi.-address and a writing .psi.-address for writing data of each of pixels stored in the line buffer, said writing .chi.-address obtained by adding, to a second beginning .chi.-address, the offset value stored in the offset buffer corresponding to data of said each of pixels stored in the line buffer and read out in order to be written in the video memory; and PA1 a memory controller for reading out pixel data of the first image line by line according to the reading .chi.-address and the reading .psi.-address when controlled in a reading mode, and writing data of each of pixels read out in order of the line buffer into the video memory according to the writing .chi.-address and the writing .psi.-address in a writing mode. PA1 a video memory for storing pixel data of the first and the second images; PA1 a reading address generator for generating a reading .chi.-address and a reading .psi.-address for reading out pixel data of the first image from the video memory, said reading .chi.-address beginning with a first beginning .chi.-address and incremented every time when data of a pixel are read out when data of each line of the first image are read out from the video memory; PA1 a transparent color register for storing data of a designated transparent color; PA1 a transparency discriminator for discriminating whether data of a pixel read out of the video memory are the same or not with data of the designated transparent color; PA1 a burst counter for counting an offset value of the reading .chi.-address of data of each of pixels read out of a line of the first image from said reading .chi.-address of data of a preceding pixel which are discriminated to be different from data of the designated transparent color by the transparency discriminator, said offset value initialized to one at beginning of data read-out of each line of the first image; PA1 a line buffer capable for storing pixel data of one line of the first image; PA1 an offset buffer for storing said offset value of each of pixels whereof data are stored at corresponding addresses of the line buffer; PA1 a buffer controller, said buffer controller storing data of each pixel of a line of the first image and the offset value of said each pixel into the line buffer and the offset buffer, respectively, according a line address, incrementing the line address and controlling the burst counter to initialize the offset value to one when data of said each pixel are discriminated to be different from data of the designated transparent color, and controlling the burst counter to increment the offset value when data of said each pixel are discriminated to be the same with data of the designated transparent color; PA1 a writing address generator for generating a writing .chi.-address and a writing .psi.-address for writing data of each of pixels stored in said line buffer, said writing .chi.-address obtained by accumulating, onto a second beginning .chi.-address, said offset value stored in the offset buffer corresponding to data of said each of pixels stored in the line buffer and read out in order to be written in the video memory; and PA1 a memory controller for reading out pixel data of said first image line by line according the reading .chi.-address and the reading .psi.-address when controlled in a reading mode, and writing data of each of pixels read out in order of the line buffer into the video memory according to the writing .chi.-address and the writing .psi.-address in a writing mode.
By way of the load clock, a magnification factor, `2` for example, is set in the repeat counter 902 as the reset value to be count down according to the count clock signal from the memory controller 904. Since the line pattern shift register 901 is shifted up when the count value of the repeat counter becomes `0`, the line pattern shift register 901 outputs the same bit during (the magnification factor +1) cycles, `3` cycles in the example, of the count clock, for zooming the line image.
In case the transparency flag is OFF, output of the line pattern shift register 901, that is, the repeated bit-map data is sequentially written in the video memory, according to the write enable signal WE output from the memory controller 904 and selected by the selector 908. When the transparency flag is ON, however, the selector 908 selects and outputs the output of the gate 907 instead of the write enable signal WE that becomes disable when bit logic of the repeated bit-map data is OFF, namely, indicating a transparent pixel.
Thus, line by line, bit-map data of a superimposed image are written in the video memory of the prior art, when the transparency flag is ON.
However, the superimposed image is obtained by writing in vain in the prior art, as above described, the bit-map data indicating transparent pixels of the image, wasting unnecessary processing time as much as needed for writing substantial data indicating pixels to be overwritten.